Semiconductor manufacturing processes must balance competing goals of cost, yield, and performance. While market demands drive manufacturers to reduce costs, improved system performance drives ever-tighter component tolerances. In many applications, the system performance requirements exceed what can be attained in a cost effective manufacturing process.
Similar issues exist in the manufacture of power supply components, for example, the variations in parametric distributions of discrete devices such as VDMOS, IGBTs, and vertical power diodes limit efficiency and switching speed in system designs.
Two primary design parameters of interest to power supply designers are the threshold voltage (Vt) and gate resistance of the switching VDMOS device. Variations in Vt and gate resistance determine system timing constraints that propagate into overall power supply efficiency ratings for the circuit utilizing the device. Tighter and more accurate control of Vt and gate resistance distributions provides many advantages. For example, some of these advantages include closer system timing, reduction in guard bands, lower switching losses, and increased efficiency. There are several device parameters of this nature where the absolute value of the parameter is not as important as the width of the variation observed for the parameter. Tighter controls of these distributions would allow the designer the flexibility to make tradeoffs in the system design, improving a particular performance characteristic as needed for a particular application.
Various techniques have been employed over the years to tighten parametric distributions from a cost effective manufacturing process, but none have been completely satisfactory.
One solution of the prior art has been to concentrate on low cost processing, test the resulting components, and sort the manufactured devices into various parametric distribution categories and to choose only those which are in an acceptable range. However, this approach raises cost because large numbers of parts from the overall population outside the distribution range must be discarded.
Another approach of the prior art has been to modify the design of the components slightly to allow trimming with a laser or other post-fabrication techniques to shift large numbers of the parts into a desired parametric range. However, this method has not been successfully applied to vertical semiconductor devices. The reason that trimming techniques are difficult to apply to vertical semiconductor devices is because the internal units making up the vertical device all have a common connection on the bottom side of the wafer. For example, the bottom side of the wafer for a VDMOS is the common drain terminal for all internal units making up the device. The bottom side of the wafer for an IGBT is the common collector terminal for all internal units making up the device. In order to implement trimming on devices like these with common terminals, novel techniques such as those described in the present invention can be utilized.